Low power intracardiac electrogram classification using analogue VLSI

A system has been developed for the classification of intracardiac electrograms (ICEG). The system is comprised of an analogue VLSI neural network, an implantable cardioverter defibrillator (ICD) and a PC based software training environment. Analogue implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network architecture reduces the impact of noise, drift and offsets inherent in analogue approaches. The neural network chip is a 10:6:3 multilayer perceptron with on chip digital weight storage, a bucket brigade input to feed the ICEG to the network and has a winner take all circuit at the output. The chip was implemented in 1.2 /spl mu/m CMOS and consumes less than 200 nW maximum average power in an area of 2.2/spl times/2.2 mm/sup 2/. The network was trained in loop with the ICD in the signal processing path. Results are presented, demonstrating the advantages of combining neural network and and low power analogue circuit techniques by distinguishing certain dangerous arrhythmia, not currently possible in existing ICDs.