A compact cell design for a multiport register file

Intended for generated layout in embedded designs, an 11-transistor design gives one write port and three read ports. Single-sided writing and reading are done by overpowering weak feedback in the memory flip-flop's and output data latches. Transistors are scaled and layout developed to form 64-word by 16-column blocks in 0.8 /spl mu/m CMOS. The four-fold decoder and I/O requirements are partially integrated into the layout.