An efficient selftimed adder design

Existing adders use a horizontal carry propagation scheme to converge to a sum. Horizontal carry propagation inhibits the exploitation of the potential parallelism inherent in the process of addition. By using a vertical carry propagation scheme and self timing, this parallelism can be easily exploited. In the work presented here, we examine one such vertical boolean scheme for carry propagation and its implementation using self timing. The average speed of a n-bit adder thus implemented approaches O(log n) and has a hardware complexity of only O(n).