Optimized placement of boundary scan circuitry on semi-custom ASICs

This paper presents strategies for an optimized placement of Boundary Scan test circuitry on semi-custom ASICs. It includes rules for an optimized partitioning of the BS Logic into different logical blocks as well as rules for an area-optimized implementation of these blocks. It exemplifies that Boundary Scan test of semi-custom ASICs can be feasible regardless of complexity and fabrication volume.