Efficient Mapping and Functional Verification of Parallel Algorithms on a MultiüContext Reconfigurable Architecture

Parallel multiücontext reconfigurable architectures provide very attractive platforms with respect to computational performance and reconfigurable features. Today's challenge is the exploitation of this reconfigurable and computational potential to ascertain efficient solution for mapping applications onto these architectures. The demand for appropriate tools is evident. In this paper we provide a combination and a mutual adaption of two separate tools to create a continuous design flow for parallel multiücontext reconfigurable architectures. Especially we present the interaction of a parameterized mapping tool for mapping compute intensive algorithms on processor arrays and a subsequent verification of the mapping results using the Configurable Reconfigurable Core (CRC) architecture model. The SystemC implementation of the CRC model leads to a cycle accurate functional simulation of the realization. Using this continuous design flow we derive an efficient realization of the edge detection algorithm (EDA) on a parallel multiücontext reconfigurable architecture. We describe in detail how the parallel realization of the EDA has to be translated in a specification for programming the CRC model.