Design of a 30 MHz, 32/16/8-points DCT processor with Phideo

This paper describes the VLSI implementation of a 30 MHz DCT processor which is able to perform 8-point, 16-point or 32-point DCT operations. The design is done using the Phideo design methodology and tool set. The paper shows how tools like those in the Phideo suite help the designer to evaluate design decisions. The interaction with the tools is at a high level of abstraction, and details of the implementation like clock level timing and control are filled in by the tools.