Architecture of queued-free crossbar for on-chip networks

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. So on-chip communication requirements of many systems are best served through the deployment of a regular chip-wide network. This paper presents the design of a crossbar for network router for such applications. Simulations illustrate how the performance and area of whole router can extremely depend on the performance of crossbar.