Improving reliability for bit parallel finite field multipliers using Decimal Hamming

Technology evolution dictates ever increasing density of transistors in chips, lower power consumption and higher performance. In such environment occurrence of multiple-bit upsets (MBUs) is a concern. That, together with the presence of fault-related attacks in cryptographic Hardware act as our motivation. The outcome of which, being presented in this paper, is a systematic method for designing multiple error correction multipliers for finite fields or GF(2
^m
). We use a variation of Hamming Codes referring to as Decimal Hamming to achieve this. We have shown that out technique can improve dramatically the reliability of a bigger multiplier by using our technique in conjunction with a series of smaller multipliers.