A 12b 50 MS/s 21.6 mW 0.18 $\mu$m CMOS ADC Maximally Sharing Capacitors and Op-Amps

A 12b 50 MS/s 0.18 μ m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18 μ m CMOS process demonstrates the measured differential and integral nonlinearities within 0.53 LSB and 2.09 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 60.6 dB and a maximum spurious-free dynamic range of 69.4 dB at 50 MS/s. The ADC with an active die area of 0.93 mm
²
consumes 21.6 mW at 50 MS/s and 1.8 V.