A 54000-gate ECL array with substrate power supply

A sub-100-ps, 54000-gate ECL array with substrate power supply has been developed on a 64-mm/sup 2/ die. Gate density of 1160 gate/mm/sup 2/ is achieved by the newly developed 'CUBE' (Chip with Upside and Backside Electrodes) technology which enables a five-layer interconnection structure including heavily doped substrate and a polycide layer in addition to the conventional three metal layers. Gate delay of 96 ps with 2.4-mW power dissipation is obtained using double-polysilicon self-aligned transistor technology. The features of this technology are (1) high-density LSI resulting in improved interconnection delay and smaller chip size, (2) small voltage drops of power supply on the chip, and (3) an increased number of signal pads by eliminating V/sub EE/ pads from the top side of the chip.<
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