Advanced multi-high-operation-voltage I/O device design for 32nm gate-first HiK MG technology

This paper presents the advanced I/O device design for 32 nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done on the I/O composite gate dielectric stack to improve TDDB Vmax. By using advanced junction engineering, 3.3 V device Isubmax is reduce by 30-40% without Ion degradation based on TCAD simulation guideline. At the same time, 2.5 V device drive current and DIBL performance are maintained without degradations. Reliability stress testing result further confirms the inline electrical result with same trend. 3.3V I/O TDDB, HCI, and BTI results are reported.