Three versions of a digital hardware implementation of a multi-layer perceptron in 0.7 /spl mu/ CMOS-design

In this paper, three versions of an implementation of a multi-layer perceptron as a neural ASIC are presented. A fully parallel version with 9 neurons as a fast version, a version with sequential processing inside the neurons, and a version with one fast neuron which is multiplexed. The three versions are compared in size and speed.