Instruction scheduling for the HP PA-8000

The PA-8000 is capable of reordering independent operations at run time, a task normally performed only by the instruction scheduler in the compiler. This paper presents some of the unique issues faced by an instruction scheduler for the PA-8000. Several features of the micro-architecture are presented along with the heuristics used in the production compiler to model that feature. These features include latency, resource constraints, instruction polarity cache interfaces, and memory dependences. The performance results in the paper show that instruction scheduling remains an important compiler optimization, even for out of order machines.