Testability insertion in behavioral descriptions

A new synthesis-for-testability approach is proposed that uses control points at branch conditions to improve testability. Hard-to-control loops are identified through analysis of the control-data flow graph, and control points are added at the exit conditions of these loops. Test statements are also inserted if necessary to allow hard-to-control variables to be directly controllable from existing primary inputs. Implementation of the proposed techniques using the HLSynth92 and HLSynth95 benchmark circuits results in significant improvements in fault coverage and reductions in test set size and test generation time. Furthermore, the impact on area and performance is minimal, and the ability to do at-speed testing is not affected.