A multithreaded architecture for the efficient execution of vector computations within a loop using status field

This paper presents the design of a high performance MULVEC(M_U_L_tithreaded architecture for the V_E_ctor C_omputations), as a building block of massively parallel processing systems. MULVEC comes from the synthesis of the dataflow model and the extant superscalar RISC microprocessor. MULVEC reduces, using a vector wait queue and status field of each vector data, the number of synchronization, context switching, network traffic, and so on in case of repeated vector computations within the same thread segment. And if vector operand in one statement is more than three, MULVEC can be computed by non-strict method. After program having been simulated on the SPARC V9(super scalar bit RISC microprocessor), the performance (execution time of example program) of uniprocessor and MULVEC according to the different number of nodes are analyzed. The performance of MULVEC according to the different number of nodes are analyzed for the several programs.