Multiplier-free realizations for FIR multirate converters based on mixed-radix number representation

We propose some realizations of FIR multirate converters. They are based on mixed-radix signed-digit number representation in conjunction with periodically time-varying (PTV) coefficients. These realizations have desirable properties of low complexity and regularity with simple processing elements that are suitable for easy VLSI layout. By varying some parameters, these realizations also provide a tradeoff between hardware and clock speed (or throughput). The PTV coefficients are restricted to the set {0,/spl plusmn/1} or {0,/spl plusmn/1,/spl plusmn/2} so that hardware multipliers are not needed. The coefficient precision of these proposed structures can be made as high as desired by appropriate choices of the parameters. However, the disadvantage is that a more complex timing control is required. Several examples are presented.