A scalable resistor-less PLL design for PowerPC/sup TM/ microprocessors

A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 /spl mu/m, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results show the response of the PLL to power supply and input clock modulation.