A monolithic 16-bit A/D converter

a 16-bit successive-approximation-type monolithic A/D converter is described. In the internal D/A converter a dynamic current divider based on dynamic element matching is used to obtain the required high accuracy of the six most significant bits. To construct the ten least significant bits a master-slave ladder and passive divider network based on emitter scaling of transistors is used. The successive approximation register (SAR) is capable of achieving high-speed conversion without the use of clock-controlled logic circuits. The conversion time is about 15 /spl mu/s. Both the linearity and differential linearity errors are less than 0.0015% FSR. The chip is processed in a standard p-n junction isolated 3 /spl mu/m bipolar technology and the die size is 5.12/spl times/6.12 mm/sup 2/.