A systolic linear array for modular multiplication

In this paper, a novel systolic, linear-array modular multiplier is presented which ideally performs the algorithm of P.L. Montgomery (1985). The total execution time for an n-bit modular multiplication is 4n+1 cycles. With only one full adding in one pipeline stage and the purely nearest neighbor communication, it can operate at a high clock frequency. On the other hand, every processing element is simple, mainly consisting of one full adder and five flip-flops. For n-bit modular multiplication, the cost of implementation is 29n gates. So our designed systolic array for modular multiplication is a speed and area efficient system suitable for the VLSI implementation of modular exponentiation which is a kernel operation used in many public-key cryptosystems such as RSA. With clock frequency of 200 megahertz which is practical in 0.8 /spl mu/m CMOS processing, the throughput can be 64k bits per second.