A chip architecture for 2.048 Mbits/s PDH/SDH mapping/desynchronisation

In this paper, a chip architecture for PDH/SDH multiplexing/demultiplexing is presented, including mapping/desynchronisation and the 1+1 protection transmission/reception. The one-step mapping scheme is used to insert/extract 21 tributary units of 2.048 Mbits/s directly into/from STM-1 frame. The time slot a VC-12 occupies in C-4 can be programmed by an external CPU. Programmable control mechanism allows the user to have a leaking period up to 34952 multi-frames and an error of 0.0167UI only at low end desynchronisation output.