Design of Polarization De-Multiplexer and PMD Compensator for 112 Gb/s Direct-Detect PDM RZ-DQPSK Systems

The design of a polarization de-multiplexer and a polarization mode dispersion compensator (PMDC) for direct-detect polarization division multiplexed (PDM) return-to-zero differential quadrature phase shift keying (RZ-DQPSK) systems are studied in detail. The impact of polarization dependent loss is studied in polarization de-multiplexers with different error detection configurations for both bit-aligned and bit-interleaved PDM systems. The level of the clock frequency of the combined pulse train of the two polarizations is proposed as the error signal for the PMDC. It enables the PMDC to work in the cancellation mode. Two separate control loops are proposed for the polarization de-multiplexer and the PMDC to allow them to work independently. The DGD tolerances for the one-stage and two-stage PMDC are measured and discussed. Finally the glitch problem in the polarization tuning algorithm is studied. An advanced dithering algorithm and the corresponding architecture of the polarization controller are proposed to solve the glitch problem.