Enhancement of TFET performance using dopant profile-steepening implant and source dopant concentration engineering at tunneling junction

All-Silicon Tunneling Field Effect Transistors (TFETs) with relatively high I
_on
values were fabricated by inserting an N
⁺
pocket between source and channel to achieve sharpening or steepening of the source dopant profile. The source-side pocket or Dopant Profile Steepening Implant (DPSI) can be tuned to engineer the junction abruptness, boost the lateral electric field at the tunnel region, and reduce the tunneling width for I
_on
enhancement. By designing the DPSI dose and energy, we demonstrate that further enhancement in I
_on
values can be achieved.