Silicon npn bipolar transistors with indium-implanted base regions

Silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF
₂
implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G/sub b/) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h/sub fe/) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h/sub fe/-V/sub A/ product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h/sub fe//spl ap/1600, excellent collector current saturation characteristics, an Early Voltage of V/sub A//spl ap/10 V, h/sub fe/-V/sub A/ product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV/sub EBO//spl ap/9.6 V, and a cut-off frequency of f
_T
=17.8 GHz.