VLSI Circuits for Accurate Motion Estimation

This paper presents VLSI circuits for Variable Block-Size Motion Estimation based on the Multiplication-Free Weighted SAD. Comparisons with existing SAD-based circuits demonstrate that higher accuracy is achieved without compromising speed performance, but resources requirements can significantly increase. Using a 90 nm 1 V CMOS technology, a running frequency higher than 1 GHz and an average power consumption lower than 100 uW/MHz are reached.