Topography and Deformation Measurement and FE Modeling applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

Topography and Deformation Measurement and FE Modeling were applied for characterization of the warpage vs. temperature behavior of several different die stacks, with or without Through Silicon Vias, for sample temperatures from 25°C…250°C. The warpage behavior is of fundamental importance for the lifetime and reliability expectation of the stack.