A fully differential class-AB switched-current integrator for signal processing

A switched-current integrator is designed with a 1.2-/spl mu/m CMOS process. The use of fully differential and complementary topology also enables class-AB operation in the circuit. Without sacrificing speed, the designed circuit reduces the clock-feedthrough error more than 20 dB compared to a single-transistor SI-cell. With the designed integrator, a fully differential sixth-order switched-current ladder filter with transmission zeros is realized. The designed circuit has a 10-MHz clock with an approximately 600 kHz corner frequency. The measurements show comparable performance to single-ended SC- and active-RC-filters with smaller die area and fabrication costs.