SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

The reliability and performance of SRAM are highly dependent on the cell stability, and the stability is affected by parasitic resistances in a memory array. The parasitic resistances result in a correlative behavior of the cells and are difficult to analyze and measure in a memory array. This topic has been rarely discussed in the literature. In this paper, the correlative behavior is analyzed by trajectories in a phase diagram composed by cell storage nodes. Electrical probing is done by the data holding test. The validity of the analysis and the probing method is confirmed by the measurements on a 0.8-/spl mu/m 1-Mb CMOS SRAM. An aspect of the cell scaling with attention to the parasitic resistance is also discussed.