Exploring parallelism during processor design space exploration

To exploit the spatial parallelism within target applications, various processor architectures are proposed. However, to estimate the scope of parallelism from high-level application remains a daunting task. A re-targetable as well as efficient High-Level Language (HLL) compiler is needed for that purpose. Building such a compiler in the early phase of processor modeling is extremely difficult. This paper proposes efficient techniques to uncover fine-grained and coarse-grained parallelism opportunities in a processor without depending on advanced compiler support. The techniques are built upon an Architecture Description Language (ADL)-driven processor exploration framework, which gives feedback to the designer on various performance aspects in the design exploration phase. Experimental studies with modern embedded applications are presented to validate the importance of this work.