An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The proposed timing generator has been mapped into a 1.0 μm CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size of 150 ps. Used as a TDC device a RMS error of 76 ps has been obtained.