A 900-MHz RF front-end with integrated discrete-time filtering

Discrete-time analog filters, rather than off-chip components, have been used to perform frequency selection and down conversion in the integrated front-end for a 900-MHz RF receiver. The first stage of frequency down conversion is implemented with a subsampling switched-capacitor sample-and-hold circuit clocked at 78 MHz. Subsequent stages of discrete-time filtering are realized using switched-capacitor biquadratic filters. An experimental prototype of the front-end had been integrated in a 0.6-/spl mu/m BiCMOS technology. The circuit provides a system gain of 36 dB and 32 dB suppression of interfering channels over a 40 MHz bandwidth. Referred to the system input, the third-order intercept-point is -16 dBm, and the spot input-referred noise is -82 dBm over a 30 kHz bandwidth. The experimental circuit dissipates 90 mW from a 3.3-V supply and occupies an active area of 1.9/spl times/1.9 mm/sup 2/.