Integration and 3D fabrication techniques to nanoscale-tip silicon high-aspect-ratio microprobe arrays

We developed integration and three-dimensional (3D)-fabrication techniques to nanoscale-tip silicon-microprobe arrays for multiple electrical nano-measurement systems with a high aspect ratio. Vapor-liquid-solid (VLS) grown vertically-aligned 120¿m-length silicon microprobe arrays (2¿m-diameter), each with nanoscale-tip by controlling the silicon-etching (less than 100-nm-diameter, radius of curvature 50nm), have been integrated with IC-processed interconnections. Subsequently, the nanotip silicon probe is entirely covered with Pt/Ti and encapsulated with an insulator, SiO
₂
. In addition, herein we proposed the use of a spray-coating of photoresist and cycled etchings of the photoresist/SiO
₂
at the probe-tips. Consequently, the nanotips can precisely be patterned and etched, resulting in the exposed Pt/Ti/silicon-nanotip with a controlled height of 2¿m.