Surface analysis and characterization of large printed-circuit-board circuitization process steps

We describe our use of surface-analysis techniques to characterize problems encountered in 1980–1981 in the fabrication of large printed circuit boards for the IBM 3081 processor unit. XPS, AES, SAM, SEM, and optical microscopy techniques were used. The two major areas addressed were (a) corrosion at a photoresist/Cu foil interface during electroless Cu plating of circuit lines which resulted in defects in subsequently formed Cu lines, and (b) surface-chemical aspects of a “single-seed” colloidal Pd/Sn catalytic initiation of electroless Cu plating onto epoxy surfaces. The corrosion mechanism responsible for the line defects was identified, and corrective actions suggested. Changes in surface composition (Pd/Sn ratio), and surface chemical state (Pd
⁰
/Pd
²⁺
,Sn
⁰
Sn
^2+,4+
) as a function of process step were correlated with plating effectiveness and led to a means of increasing the surface Pd
⁰
/Sn ratio by as much as an order of magnitude.