Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”

Hash functions are widely used in information security and cryptography. They are used in countless applications such as message authentication codes (MAC), Digital Signatures (DS) and mobile trusted modules (MTM). Serious attacks have been reported against cryptographic hash algorithms, including SHA-1. Because the SHA-1 and SHA-2 families share a similar design, the National Institute of Standards and Technology (NIST) in 2007 decided to start a world-wide development process for choosing the next secure hash standard SHA-3. A pivotal part of the process is an open competition for bringing forward new and secure cryptographic hash functions. The Blue Midnight Wish hash function is one of the second round candidates for the SHA-3 competition. In this paper, we describe low area FPGA and ASIC implementations for the Blue Midnight Wish compression function with digest size of 256 bits (BMW-256). Using Xilinx FPGA platform Virtex 5 "XC5VLX30", we implemented BMW-256 using 1986 slices (including the internal memory), and using only 122 slices for an implementation that uses external memory. By using 0.8 μm CMOS standard cell library the ASIC implementation of BMW-256 takes approximately 13.5 Kgates (including the internal memory), and only 4 Kgates for an implementation that uses external memory.