Router microarchitecture and scalability of ring topology in on-chip networks

On-chip networks are critical to the scaling of future multicore processors. Recent multicore processors have adopted ring topologies because of its simplicity and high bandwidth. In this paper, we first describe a bufferless router microarchitecture for an on-chip network ring topology. We propose to extend the bufferless router with an extra buffer entry to create a lightweight router microarchitecture. The proposed microarchitecture approaches ideal latency by reducing the microarchitecture complexity through minimizing the amount of buffers and simplifying switch allocation. We describe how the proposed lightweight microarchitecture does not need additional virtual channels to break routing deadlock. The scalability of the ring topology is presented as the network size increase. Although the ring topology has larger hop count with larger network diameter, lower per-hop router latency and no serialization latency results in lower latency for the ring topology compared to a 2D mesh topology. However, the wide channels in a ring topology creates bandwidth fragmentation which results in poor bandwidth utilization for short packets, compared to a 2D mesh topology, and can limit the scalability of the ring topology.