Low-phase-noise frequency synthesizer for the trapped atom clock on a chip

We report on the realization of a 6.834-GHz synthesis chain for the trapped atom clock on a chip (TACC) that is being developed at LNE-SYRTE. The chain is based on the frequency multiplication of a 100-MHz reference signal to obtain a signal at 6.4 GHz. It uses a comb generator based on a monolithic GaAs nonlinear transmission line. This is a novelty in the fabrication of high-stability microwave synthesizers. Measurements give a low flicker phase noise of -85 dBrad
²
/Hz at 1-Hz offset frequency and a white phase noise floor < -115 dBrad
²
/Hz. Based on these results, we estimate that the performance of the synthesizer is at least one order of magnitude better than the stability goal of TACC. This ensures that the synthesizer will not be limiting the clock performance.