A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm

A prototype 32/spl times/32 array processor fabricated in 2-/spl mu/m charge coupled devices (CCD)/CMOS technology implementing the multiscale veto edge detection algorithm is presented. In this algorithm, differences between pixel values are computed in the original image, as well as after applying a series of smoothing filters of varying spatial scales. An edge exists between two pixels only if the magnitude of their difference is greater than a given threshold for all levels of smoothing tested. This algorithm maps particularly well to implementation as a focal plane processor as it requires only nearest neighbor communication. The CCD array performs the functions of image acquisition, charge loading and removal, and image smoothing. Analog circuits between each pair of pixels in the array compute the absolute value of difference between neighboring values and compare it to a global threshold. These circuits have been designed to allow reliable discrimination of differences from /spl sim/3.1% to /spl sim/10.1% of full scale range and thus meet the performance requirements of many machine vision applications.