High-performance circuit testing with slow-speed testers

We propose a method of testing high-speed digital devices whose clock frequency exceeds the capability of the test equipment. The circuit is designed such that a controllable delay is introduced in the timing paths during test. With the added delay, the maximum operating frequency is lowered to a rate which is within the capability of the ATE. The delay circuit is so designed that its function is also testable. In an illustrative design with single clock, the controllable delay is incorporated within a master-slave flip-flop. The control of delay is then achieved by manipulation of the duty-cycle of the clock waveform. In a two-clock system, no modification of the flip-flop is required and the delay is varied by skewing one clock signal with respect to the other.