Simulation of transients in VLSI packaging interconnections

An approach to electrical analysis of VLSI packaging interconnections using computer simulation is presented. The corresponding simulation software developed during the course of research on VLSI interconnections conducted at the University of Arizona is described. Examples of application to prototypical interconnections (two transmission line systems joined by a lumped parameter network of bipolar and MOS transistors) are provided. The simulation results for the above examples are presented and analyzed. The current status of the work is discussed and directions of future research delineated.<
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