Mixed-mode timing simulation for accurate CMOS bridging fault detection

A bridging fault simulator of CMOS VLSI circuits with timing information is described. It can detect delay as well as logic faults. A realistic resistive two-line bridging fault model is used. Mixed-mode bridging fault simulation without timing information is performed first to detect those faults that cause logic errors so as to reduce the fault set. Test vector selection, and mixed-mode timing simulation techniques are then used to speed up the simulation. Simulation results of some of the ISCAS 89 sequential benchmark circuits are given.