An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling

A CMOS serial link is described that uses a digital PLL with 3/spl times/ over-sampling to recover both clock and data. An implementation with 0.6 /spl mu/m CMOS technology exhibits 800 Mbps operation with BER of less than 10E-12 for pseudo random number sequence. Chip area and power dissipation per channel at 800 Mbps are 2.1 mm/spl times/1.1 mm and 0.75 W, respectively.