PCHECK: a delay analysis tool for high performance LSI design

This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time, (2) a precise delay calculation model for resistive shielding and (3) parallel delay calculation on networked workstations. Experimental results show that the delay calculation error in the worst case is less than 20 ps and that the speed improvement when using 20 workstations is over 17 times that for a single processor.