The design of a 50 Mflop arithmetic chip for massively parallel pipelined DSP algorithms: the floating point pipeline CORDIC processor

The paper describes a high performance VLSI CORDIC arithmetic chip. It performs 15 10/sup 6/ rotations/sec (50 Mflops) and can be applied as a processing element in parallel/pipelined processor structures (systolic and wavefront arrays) for real time/high speed signal processing algorithms and matrix computation applications. The authors present a novel optimized (floating point) CORDIC algorithm, and architecture, its performance and layout. Algorithm, architecture, performance and layout are parametrized which allows automatic generation of the chip layout for any required chip performance, accuracy and dynamic range of arithmetic operations.<
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