Recursive layout generation

We present a recursive method for generating layout for VLSI chips based on integrating layout directives in the netlist description. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense BiCMOS VLSI microprocessor chips automatically.