The WASP-3 monolithic-WSI massively parallel processor

The paper is a progress report on the WASP development programme. It reports on the successful conclusion of a wafer-scale hybridisation experiment, designed as 'proof-of-principle' of the wafer stacking procedure used in the mating of WASP-3 wafers and their HDI (High Density Interconnect) layer. WASPS wafers have completed manufacture and are now undergoing final assembly prior to commencing test. The paper reviews the WASP configurable high-level interconnection strategies and gives a thorough review of the corresponding test and reconfiguration strategies.