Emitter resistance and performance trade-off of submicrometer self-aligned double-polysilicon bipolar devices

Emitter resistance dependences on emitter arsenic implant dose and diffusion temperature, emitter polysilicon film thickness and its two-dimensional effect, and in situ emitter surface cleaning with HCl gas for submicrometer self-aligned double-polysilicon bipolar transistors are described. Emitter resistance is also characterized as a function of emitter area ranging from 0.6*2.4 mu m/sup 2/ to 3.4*10.4 mu m/sup 2/. Cutoff frequency and ECL-gate delay time are compared between the devices with different emitter areas. Based on the experimental results and circuit simulations, and effects of device geometry scaling on emitter resistance and ECL circuit performance are discussed. It is predicted that an ECL-gate delay time of 35 psec with a cutoff frequency of 33 GHz can be expected at an operational current of 400 mu A by achieving the emitter-base, base-collector, and collector-substrate capacitances of 3 fF, 2 fF, and 4 fF, respectively, with a neutral base width of 40 nm and an emitter resistance of 100 Omega .<
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