On-Chip I/sub DDQ/ testability schemes for detecting multiple faults in CMOS ICs

In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be detected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adder/subtractor (CLAAS) as well as a 16-bit arithmetic logic unit (ALU). Simulation results are given.