A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication

A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-/spl mu/m CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions.