Flexible VLSI architecture of motion estimator for video image compression

A linear array architecture for a full-search block matching algorithm is proposed. It is suitable for low bit-rate video applications with a single chip realization. It uses a parallel algorithm based on the idea of partial result accumulation. Combining a serial data input with registers for a line of search window pixels and operating on them in parallel, the partial results of the candidate block distortions are obtained for all horizontal search positions, which are successively accumulated into a cyclic storage buffer. Based on this scheme, a flexible architecture can be designed for motion vector estimation of different search ranges and block sizes.