Dynamics of power MOSFET switching under unclamped inductive loading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p/sup +/ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions.