Thickness dependence of boron penetration through O/sub 2/- and N/sub 2/O-grown gate oxides and its impact on threshold voltage variation

We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O/sub 2/ or N/sub 2/O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N/sub B/, for thicknesses other than those measured. We find that the minimum t/sub ox/ required to inhibit boron penetration is always 2-4 nm less when N/sub 2/O-grown gate oxides are used in place of O/sub 2/- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t/sub ox/, incremental variations in oxide thickness result in a large variation in N/sub B/, leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10/sup 11/ cm/sup -2/.